F85226 Datasheet, PDF (38/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
8.55 IRQ Wakeup Register (I) – Index 0x51
Feature Integration Technology Inc.
F85226
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7
EN_IRQ7_W
RW VDD3V Set to 1 to enable IRQ7 to wakeup the system.
6
EN_IRQ6_W
R/W VDD3V Set to 1 to enable IRQ6 to wakeup the system.
5
EN_IRQ5_W
R/W VDD3V Set to 1 to enable IRQ5 to wakeup the system.
4
EN_IRQ4_W
R/W VDD3V Set to 1 to enable IRQ4 to wakeup the system.
3
EN_IRQ3_W
R/W VDD3V Set to 1 to enable IRQ3 to wakeup the system.
2
Reserved
R/W VDD3V Reserved
1
EN_IRQ1_W
R/W VDD3V Set to 1 to enable IRQ1 to wakeup the system.
0 EN_PWRDN_W RW VDD3V Set to 1 to enable PWRDN pin to power down or wakeup the system.
8.56 IRQ Wakeup Register (II) – Index 0x52
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7 Reserved
RW VDD3V Reserved
6 EN_IRQ15_W
R/W VDD3V Set to 1 to enable IRQ15 to wakeup the system.
5 EN_IRQ14_W
R/W VDD3V Set to 1 to enable IRQ14 to wakeup the system.
4 EN_IRQ12_W
R/W VDD3V Set to 1 to enable IRQ12 to wakeup the system.
3 EN_IRQ11_W
R/W VDD3V Set to 1 to enable IRQ11 to wakeup the system.
2 EN_IRQ10_W
R/W VDD3V Set to 1 to enable IRQ10 to wakeup the system.
1 EN_IRQ9_W
R/W VDD3V Set to 1 to enable IRQ9 to wakeup the system.
0 EN_IRQ8_W
RW VDD3V Set to 1 to enable IRQ8 to wakeup the system.
8.57 CHIPID (1) Register – Index 5Ah
Power-on default [7:0] =0000_0011b
Bit
Name
R/W PWR
7-0 CHIPID
RO VDD3V Chip ID, High byte (8’h03).
Description
8.58 CHIPID (2) Register – Index 5Bh
Power-on default [7:0] =0000_0101b
Bit
Name
R/W PWR
7-0 CHIPID
RO VDD3V Chip ID, Low byte (8’h05).
Description
F85226
33
July, 2007
V0.25P