F85226 Datasheet, PDF (11/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
11 IOCS16#
12 MEMCS16#
76 IOCHCK#
I/O_24ts
(5V-tolerance)
I/O_24ts
(5V-tolerance)
IN_ts
(5V-tolerance)
81 OWS#
IN_ts
(5V-tolerance)
103-104
LA[23:20]
106-107
I/O_{24ts_u100k}
(5V-tolerance)
108-109
111
LA[19:17]
GP23, GP22,
GP21
I/O_{24ts_u100k}
(5V-tolerance)
82 SMEMW#
O₂₄
(5V-tolerance)
83 SMEMR#
O₂₄
(5V-tolerance)
91 REFRESH#
O_{24_u100k}
(5V-tolerance)
101 BALE
102 SBHE#
112 MEMR#
113 MEMW#
I/O_{24ts_u100k}
(5V-tolerance)
I/O_{24ts_u100k}
(5V-tolerance)
I/O_{24ts_u100k}
(5V-tolerance)
I/O_{24ts_u100k}
(5V-tolerance)
Feature Integration Technology Inc.
F85226
16-bit I/O Chip Select. IOCS16# is asserted by 16-bit ISA I/O
VDD3v
devices to indicate that they support 16-bit I/O bus cycles.
VDD3v
Memory Chip Select 16. MEMCS16# is asserted by 16-bit ISA
memory devices to indicate that the memory slave supports 16-bit
accesses.
I/O Channel Check. Asserted by an ISA device indicating an error
VDD3v
condition.
VDD3v
VDD3v
VDD3v
Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate
that the current cycle can be executed as an ISA zero wait state
cycle. ZEROWS# has no effect during 16-bit I/O cycles.
Unlatched Address. The LA [23:20] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA [23:20] are outputs
when the F85226 owns the ISA Bus.
Unlatched Address. The LA [19:17] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA [19:17] are outputs
when the F85226 owns the ISA Bus.
General purpose I/O pin.
Standard (system) Memory Write. SMEMW# is asserted for
VDD3v
memory write accesses below 1MB.
Standard (system) Memory Read. SMEMR# is asserted for
VDD3v
memory read accesses below 1 MB.
VDD3v
VDD3v
VDD3v
VDD3v
Refresh Cycle indicator. REFRESH# asserted indicates that a
refresh cycle is in progress, or ISA master requests F85226 to
generate a refresh cycle. The signal is at tri-stated upon
PCIRST#.
Bus Address Latch Enable. BALE asserted indicates when the
address (SA[19:0], LA[23:17]) and SBHE# are valid. The LA
[23:17] address lines are latched on the trailing edge of BALE.
BALE is driven by low upon PCIRST#.
System Byte High Enable. SBHE# asserted indicates that
SD[15:8] will be used to transfer a byte. SBHE# is at an unknown
state upon PCIRST#.
Memory Read. MEMR# asserted indicates the current ISA bus
cycle is a memory read.
Memory Write. MEMW# asserted indicates the current ISA bus
VDD3v
cycle is a memory write.
F85226
6
July, 2007
V0.25P