F85226 Datasheet, PDF (37/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
F85226
8.51 IOH Decoder Mask Register – Index 0x3F
Power-on default [7:0] =1111_1111b
Bit
Name
R/W PWR
Description
This register is used to mask address bits (A7~A0) for specify address decoder, if
the corresponding bit of this register is set to a 1, the corresponding address
7-0 IOH_ MASK
R/W VDD3V bit(A7~A0) is ignored by the specify address decoder.
For example: If the decoding range is 0x0000 ~ 0x00FF, you can set 0x00 to
CR40, 41 and FFh to CR3F.
8.52 IOH Decoder Address Low Byte Register – Index 0x40
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
This register contains the address for KBC decoder.
CR40 Bit [7..0] are used to define low byte of specify address.
7-0
IOH_DEC
R/W VDD3V CR41 Bit [7..0] are used to define high byte of specify address.
For example: Decoding address was set to be 0x0080h when wrote 80h to CR40
and 00h to CR41.
8.53 IOH Decoder Address High Byte Register – Index 0x41
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
This register contains the address for KBC decoder.
CR40 Bit [7..0] are used to define low byte of specify address.
7-0
IOH_DEC
R/W VDD3V CR41 Bit [7..0] are used to define high byte of specify address.
For example: Decoding address was set to be 0x0080h when wrote 80h to CR40
and 00h to CR41.
8.54 Edge Detector Status Register – Index 0x50
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-1
Reserved
RO VDD3V Reserved
0
CLK_PD
RW VDD3V Set to 1 to disable SYSCLK output.
F85226
32
July, 2007
V0.25P