F85226 Datasheet, PDF (29/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
F85226
8.19 Master Setting Register – Index 1Dh
Power-on default [7:0] =0110_0011b
Bit
Name
R/W PWR
Description
7
EN_TIMEOUT R/W VDD3V Enable this bit to timeout LPC long wait when ISA bus had pull IOCHRDY to low.
6-0 TIMEOUT_VALUE R/W
VDD3V
Define the timeout value, the unit is ISA system clock. So if ISA pull IOCHRDY to
low more then this time, the device will end of the LPC long wait. (default are 100
ISA Clock)
8.20 Refresh Address Register (Low Byte) – Index 1Eh
Power-on default [7:0] =1111_1111b
Bit
Name
R/W PWR
Description
7-0 REFRESH_ADDR R/W
VDD3V
CR 1E, 1F are used to define the refresh counter repeat value: For example, if set
REFRESH_ADDR to 0x01FF, the address in refresh will increase until reach
0x01FF and then refresh address return to 0x0000.
8.21 Refresh Address Register (High Byte) – Index 1Fh
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 REFRESH_ADDR R/W
VDD3V
CR 1E, 1F are used to define the refresh counter repeat value: For example, if set
REFRESH_ADDR to 0x01FF, the address in refresh will increase until reach
0x01FF and then refresh address return to 0x0000.
8.22 Address1 Decode Mask Register – Index 20h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR_MASK1 R/W VDD3V ^{This register is used to mask address bits (A7~A0) for specify address decoder, if}
the corresponding bit of this register is set to a 1, the corresponding address
bit(A7~A0) is ignored by the specify address decoder.
For example: If the decoding range is 0x3F8 ~ 0x3FF, you can set 0x03F8 to CR21,
22 and 07h to CR20.
8.23 Address1 Decode Register (Low Byte) – Index 21h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR_DEC1 R/W VDD3V This register contains the address for specify decoder.
F85226
24
July, 2007
V0.25P