F85226 Datasheet, PDF (20/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
8. Registers Description
Feature Integration Technology Inc.
F85226
8.1 Entry Key: Write 26h to the location 4Eh ( Default ) twice will enable the following
configuration registers. Change the location to 2Eh by power-on strapping with an external
pulled-down resister on pin 128.
8.2 Configuration and Control Register – Index 03h
Power-on default [7:0] =00_100_0_s_0b (s: mean default value effect by strapping)
Bit
Name
R/W PWR
Description
7-6 ROM_SEL_TYPE R/W VDD3V 00: ROMCS# decoder address 0xF_xxxx, and 0xE_xxxx if BIOS_0E_EN set to 1
(REG03h bit0).
01: ROMCS# decoder address by define address 1 (REG2Ah, 2Bh) and define
address 2 (REG 2Eh, 2Fh).
10: ROMCS# decoder address 0xF_xxxx, and 0xE_xxxx if BIOS_0E_EN set to 1
(REG03h bit0) or ROMCS# decoder address by define address 1 (REG2Ah,
2Bh) and define address 2 (REG 2Eh, 2Fh).
11: ROMCS# decoder address 0xF_xxxx, and 0xE_xxxx if BIOS_0E_EN set to 1
(REG03h bit0) or ROMCS# decoder address by define address 1 (REG2Ah,
2Bh) and define address 2 (REG 2Eh, 2Fh).
4-2 BIOS_ROM_SIZE R/W VDD3V 000: ROMCS# decodes range 1M.
001: ROMCS# decodes range 2M.
010: ROMCS# decodes range 4M.
011: ROMCS# decodes range 8M.
100: ROMCS# decodes range 16M.
101: ROMCS# decodes range 32M.
110: ROMCS# decodes range 64M.
111: ROMCS# decodes range 1M.
2 BIOS_0E_EN
R/W VDD3V Enable ROMCS# to decode the address 0xE_XXXX.
1 BIOS_ROM_EN
R/W VDD3V Enable ROMCS# to decode address.
0 BIOS_WR_EN
R/W VDD3V When BIOS_ROM_EN is enabled, sets this bit to protect BIOS write.
F85226
15
July, 2007
V0.25P