F85226 Datasheet, PDF (32/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

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Feature Integration Technology Inc.
F85226
8.32 ROM2 Decoder Mask Low Byte Register – Index 0x2C
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ROM_MASK2
The register CR2C, 2D are used to mask address bits (A19~A4) for specify address
decoder, if the corresponding bit of this register is set to a 1, the corresponding
R/W VDD3V _{address bit(A19~A4) is ignored by the specify address decoder.}
For example: If the decoding range is 0xF_FFFX ~ 0xF_E00X, you can set
0xF_FFFF to CR2E, 2F and ffh to CR2C, 01h to CR2D.
8.33 ROM2 Decoder Mask (High Byte) Register – Index 0x2D
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ROM_ MASK2
The register CR2C, 2D are used to mask address bits (A19~A4) for specify address
decoder, if the corresponding bit of this register is set to a 1, the corresponding
R/W VDD3V _{address bit(A19~A4) is ignored by the specify address decoder.}
For example: If the decoding range is 0xF_FFFX ~ 0xF_E00X, you can set
0xF_FFFF to CR2E, 2F and ffh to CR2C, 01h to CR2D.
8.34 ROM2 Decoder Address (Low Byte) Register – Index 0x2E
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
This register contains the address for specify decoder.
CR2E Bit [7..0] are used to define low address[11:4].
7-0 ROM_DEC2
R/W VDD3V _{CR2F Bit [7..0] are used to define high address[19:12].}
For example: Decoding address was set to be 0x5_5AAXh when wrote AAh to
CR2E and 55h to CR2F.
8.35 ROM2 Decoder Address (High Byte) Register – Index 0x2F
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ROM_DEC2
This register contains the address for specify decoder.
CR2E Bit [7..0] are used to define low address[11:4].
R/W VDD3V _{CR2F Bit [7..0] are used to define high address[19:12].}
For example: Decoding address was set to be 0x5_5AAXh when wrote AAh to
CR2E and 55h to CR2F.
F85226
27
July, 2007
V0.25P