F85226 Datasheet, PDF (30/44 Pages) Feature Integration Technology Inc. – LPC to ISA Bridge

Fintek
Feature Integration Technology Inc.
F85226
CR21 Bit [7..0] are used to define low byte of specify address.
CR22 Bit [7..0] are used to define high byte of specify address.
For example: Decoding address was set to be 0x3F5h when wrote F5h to CR21
and 03h to CR22.
8.24 Address1 Decode Register (High Byte) – Index 22h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR_DEC1
This register contains the address for specify decoder.
CR21 Bit [7..0] are used to define low byte of specify address.
R/W VDD3V _{CR22 Bit [7..0] are used to define high byte of specify address.}
For example: Decoding address was set to be 0x3F5h when wrote F5h to CR21
and 03h to CR22.
8.25 Address2 Decode Mask Register – Index 23h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR_MASK2
This register is used to mask address bits (A7~A0) for specify address decoder, if
the corresponding bit of this register is set to a 1, the corresponding address
R/W VDD3V _{bit(A7~A0) is ignored by the specify address decoder.}
For example: If the decoding range is 0x3F8 ~ 0x3FF, you can set 0x03F8 to CR24,
25 and 07h to CR23.
8.26 Address2 Decode Register (Low Byte) – Index 24h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
This register contains the address for specify decoder.
CR24 Bit [7:0] are used to define low byte of specify address.
7-0 ADDR_DEC2 R/W VDD3V _{CR25 Bit [7:0] are used to define high byte of specify address.}
For example: Decoding address was set to be 0x3F5h when wrote F5h to CR24
and 03h to CR25.
8.27 Address2 Decode Register (High Byte) – Index 25h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-0 ADDR_DEC2
This register contains the address for specify decoder.
R/W VDD3V _{CR24 Bit [7..0] are used to define low byte of specify address.}
CR25 Bit [7..0] are used to define high byte of specify address.
F85226
25
July, 2007
V0.25P