GMS81C7216 Datasheet, PDF (85/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
22. RESET
The GMS81C7208/16 has two types of reset generation proce-
dures; one is an external reset input, the other is a watch-dog tim-
er reset. Table 22-1 shows on-chip hardware initialization by
reset action.
V_CC
7036P
10kΩ
+
10uF
to the RESET pin
Figure 22-1 Simple Power-On Reset Circuit.
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt
Trigger. A reset in accomplished by holding the RESET pin low
for at least 8 oscillator periods, within the operating voltage range
and oscillation stable, it is applied, and the internal state is initial-
ized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods
are required to start execution as shown in Figure 22-2.
Internal RAM is not affected by reset. When V_DD is turned on,
the RAM content is indeterminate. Therefore, this RAM should
Oscillator
(X_IN pin)
RESET
On-chip Hardware
Program Counter (PC)
G-Flag (G)
Operation Mode
Peripheral Clock
Watchdog Timer
Control Registers
Low Voltage Detector
Initial Value
(FFFF_H) - (FFFE_H)
0
Main Operating Mode
On
Disable (Because the Watch
timer is disabled)
Refer to Table 8-1 on
page 24
Enable
Table 22-1 Initializing Internal Status by Reset Action
be initialized before read or tested it.
When the RESET pin input goes to high, the reset operation is re-
leased and the program execution starts at the vector address
stored at addresses FFFE_H - FFFF_H.
A connection for simple power-on-reset is shown in Figure .
1234567
ADDRESS
BUS
DATA
BUS
?
??
?
FFFE FFFF Start
?
? ? ? FE ADL ADH OP
Stabilization Time
t_ST = 62.5mS at 4.19MHz
RESET Process Step
1
t_ST = _{fMAIN ÷1024} x 256
Figure 22-2 Timing Diagram after RESET
MAIN PROGRAM
22.2 Watchdog Timer Reset
Refer to “18. LCD DRIVER” on page 65.
FEB. 2005 Ver 1.04
81