GMS81C7216 Datasheet, PDF (55/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
value in the timer counter register (T0,T1), to be captured and
stored into registers CDRn (CDR0, CDR1), respectively. After
capture, the Timer counter register is cleared and restarts by hard-
ware. At this time, reading the address E1_H as a CDR0, not T0.
T0, TDR0, CDR0 are located at same address. The other
CDR1~CDR3 are same. Refer to timer registers of page 26.
It has three transition modes: “falling edge”, “rising edge”, “both
edge” which are selected by interrupt edge selection register
IEDS. Refer to “17.4 External Interrupt” on page 63. In addition,
the transition at INTn pin generate an interrupt.
Note: The CDRn and Tn are in same address.In the cap-
ture mode, reading operation is read as CDRn, not Tn be-
cause addressing path is opened to the CDRn.
TM0
TM1
IEDS[1:0]
7
6
5
4
3
2
1
0
-
- CAP0 T0CK2 TB0TCCKL1 T0CK0 T0CN T0ST
X
X
1
X
X
X
X
X
- 16BIT0 - CAP1 TB1TCCKL1 T1CK0 T1CN T1ST
X
1
0
1
1
1
X
X
X means don’t care
ADDRESS: 0E0_H
INITIAL VALUE: 00_H
ADDRESS: 0E2_H
INITIAL VALUE: 00_H
01
INT0 PIN
10
11
Edge Detector
T0CK[2:0]
EC0 PIN
SCMR[1:0]
f_XIN
reserved
0X ^fEX
1X
111
÷ 2048 ₁₁₀
÷ 512
101
÷ 128
100
÷ 32
011
÷8
010
÷4
001
÷2
000
MUX
T0CN
INT0IF
MSB
16 BITS
LSB
CDR1
capture
clear
T1
CDR0
T0ST ^{0: Stop}
1: Clear and start
clear
T0
INT0
INTERRUPT
Comparator
T0IF
TIMER 0
INTERRUPT
TDR1
TDR0
COMPARE DATA
Figure 13-11 16-bit Capture Mode
13.4 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the
timer register is being run will 16 bits. Configuration is shown in
Figure 13-11.
FEB. 2005 Ver 1.04
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