GMS81C7216 Datasheet, PDF (78/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
WTMR
- R/W -
- WTEN -
- R/W R/W R/W R/W
- WTIN1 WTIN0 WTCK1 WTCK0
ADDRESS: 0EF_H
INITIAL VALUE: -0--_0000_B
Watch Timer Count Enable
0: Disable
1: Enable
Clock Source Selection
00: Reserved
01: Main Clock (f_XIN ÷ 128)
10: Main Clock (test purpose in factory)
11: -
Watch Timer Interrupt Interval Selection
00: 16Hz
01: 4Hz
10: 2Hz
When
f_XIN = 4.19MHz
11: -
WDTR
-
- R/W R/W R/W R/W R/W R/W
-
-
-
WDEN WDCK1 WDCK0 WDOM WDCLR
ADDRESS: 0DF_H
INITIAL VALUE: --01_0010_B
Watchdog Timer Count Enable
0: Disable
1: Enable
Clear Bit
0: Normal operation
1: Clear and starts counting
Output Mode
0: Interrupt Request
1: Reset CPU
Watchdog Timer Interrupt Interval Selection
00: 2 sec.
01: 1 sec.
10: 0.5 sec.
When
f_XIN = 4.19MHz
11: 0.25 sec.
Figure 19-2 WTMR, WDTR: Watch Timer and Watchdog Timer Data Register
Example: Sets the Watchdog Timer Detection Time to 1 SEC at 4.19MHz
LDM WTMR,#0100_1000B;Select sub clock as an input source
LDM WDTR,#0001_0111B
SET1 WDCLR
:
Within 0.7:5 sec.
:
:
SET1 WDCLR
:
Within 0.7^:5 sec.
:
:
SET1 WDCLR
;Clear counter
;Clear counter
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDEN (bit 4 in CKCTLR)
to “1”. WDEN is initialized to “1” during reset and it should be
clear to “0” disable.
Example: Enables watchdog timer for Reset
:
LDM WTMR,#0100_XXXXB;WTEN ← 1
LDM WDTR,#00X1_XX11B;WDEN ← 1
:
The watchdog timer is disabled by clearing either bit 4 (WDEN)
of WDTR or bit 6 (WTEN) of WTMR. The watchdog timer is
halted in STOP mode and restarts automatically after STOP mode
is released.
Clearing 2-Bit Binary Counter of the Watchdog
Timer
The watchdog timer count the clock source as 14-bit binary
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FEB. 2005 Ver 1.04