GMS81C7216 Datasheet, PDF (70/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
18.1 LCD Control Registers
The LCD driver is controlled by the LCD control register LCR
which is shown in Figure 18-2. LCD block input the clock from
the watch timer. When LCD is operate, the watch timer much be
enabled by WTEN (bit 6 of address 0EF_H).
LCR
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
SUBM BTC LCDEN BRC DTY1 DTY0 LCK1 LCK0
ADDRESS: 0F1_H
INITIAL VALUE: 00_H
Bias Transistor Control
0: Off
1: On
LCD Display Control
0: LCD Display All Segment 0 Data Output
1: LCD Display Enable
** Caution : The bit7(SUBM) of LCR register must be set to “1”
by software because of reduction current consumption
(reset value=”0”).
Selection Frame Frequency
00: f_XIN÷2⁷÷32, 1024Hz@4.19MHz
01: f_XIN÷2⁷÷64, 512Hz@4.19MHz
10: f_XIN÷2⁷÷128, 256Hz@4.19MHz
11: f_XIN÷2⁷÷256, 128Hz@4.19MHz
Duty Control
00: 1/4 Duty
01: 1/3 Duty (SEG24 Active)
10: 1/2 Duty (SEG24, SEG25 Active)
11: Static (SEG24, SEG25, SEG26 Active)
Bias Resistor Control
0: External
1: Internal
No internal bias registers in the Emulator,
so user must select the “0”, External mode at least
during use the Emulator.
OTP and Mask MCU can use both.
R/W R/W R/W R/W
7
6
5
4
LPMR ^-
-
R6LPMR
R/W R/W R/W R/W
3
2
1
0
R5LPMR
R4LPMR
ADDRESS: 0F2_H
INITIAL VALUE:0000 0000
R4 port Selection
00:SEG0~SEG7
01:SEG4~SEG7,R40~R43
10:SEG0~SEG3,R44~R47
11:R40~R47
R5 port Selection
00:SEG8~SEG11
01:R50~R53
10:SEG8~SEG11
11:R50~R53
R6 port Selection
00:SEG16~SEG20
01:SEG20,R60~R63
10:SEG16~SEG19,R64
11:R60~R64
-
-
-
-
-
-
R/W R/W
7
6
5
4
3
2
1
0
RPR
-
-
-
-
-
- _{RPR1 RPR0}
The RPR register is used for RAM page selection.
ADDRESS: 0F3_H
INITIAL VALUE: 00_H
RAM page Instruction
PRP1
PRR0
Page 0
CLRG
X
X
Page 0
SETG
0
0
Page 1
SETG
0
1
Reserved SETG
1
0
Reserved SETG
1
1
Figure 18-2 LCD Control Register
66
FEB. 2005 Ver 1.04