GMS81C7216 Datasheet, PDF (26/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
Example: The usage software example of Vector address for GMS81C7216.
ORG 0FFE0H
DW TIMER3
DW TIMER2
DW WATCH_TIMER
DW ADC
DW SIO
DW NOT_USED
DW NOT_USED
DW INT2
DW TIMER1
DW TIMER0
DW INT1
DW INT0
DW WD_TIMER
DW BIT_TIMER
DW NOT_USED
DW RESET
; Timer-3
; Timer-2
; Watch Timer
; ADC
; Serial Interface
;-
;-
; Int.2
; Timer-1
; Timer-0
; Int.1
; Int.0
; Watchdog Timer
; Basic Interval Timer
;-
; Reset
ORG 0C000H
;
ORG 0E000H
; in case of 16K ROM Start address
; in case of 8K ROM Start address
;*******************************************
;
MAIN
PROGRAM
*
;*******************************************
;
RESET: LDM SCMR,#0
;When main clock mode
DI
;Disable All Interrupts
LDM WDTR,#0
;Disable Watch Dog Timer
LDM RPR,#1
CLRG
LDX #0
RAM_CLR: LDA #0
;RAM Clear(!0000H ~ !00BFH)
STA {X}+
CMPX #0C0H
BNE RAM_CLR
SETG
LDX #0
RAM_CLR1:
LDA #0
STA {X}+
CMPX #1BH
;DISPLAY RAM Clear(!0100H ~ !011AH)
BNE RAM_CLR1
CLRG
;
LDX #0FFH
;Stack Pointer Initialize
TXSP
;
LDM R0, #0
;Normal Port 0
LDM R0DD,#82H
;Normal Port Direction
LDM R0PU,#0
;Normal Pull Up
:
:
:
LDM TDR0,#250
;8us x 250 = 2000us
LDM TM0,#0000_1111B
;Start Timer0, 8us at 4MHz
LDM IRQH,#0
LDM IRQL,#0
LDM IENH,#0000_1110B
;Enable INT0, INT1, Timer0
LDM IENL,#0
LDM IEDS,#15H
;Select falling edge detect on INT pin
LDM PMR,#3H
;Set external interrupt pin(INT0, INT1)
EI
;Enable master interrupt
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FEB. 2005 Ver 1.04