GMS81C7216 Datasheet, PDF (64/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
.
Internal bus line
[0DA_H]
INT2
Serial
Communication
A/D Converter
Watch Timer
Timer 2
Timer 3
IRQL [0DC_H]
INT2IF
SIOIF
ADIF
WTIF
T2IF
T3IF
IRQH [0DD_H]
IENL
BIT
Watchdog Timer
INT0
INT1
Timer 0
Timer 1
BITIF
WDTIF
INT0IF
INT1IF
T0IF
T1IF
Interrupt Enable
Register (Lower byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP
I-flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
[0DB_H]
IENH
Interrupt Enable
Register (Higher byte)
Internal bus line
Figure 17-2 Block Diagram of Interrupt
R/W
IENL ^INT2E
MSB
-
IENH
-
MSB
-
-
R/W
- R/W R/W R/W R/W R/W
- SIOE ADE WTE T2E T3E
LSB
R/W R/W R/W R/W R/W
BITE WDTE INT0E INT1E T0E
R/W
T1E
LSB
ADDRESS: 0DA_H
INITIAL VALUE: 0--0 0000_B
Timer/Counter 3 Interrupt Enable Flag
Timer/Counter 2 Interrupt Enable Flag
Watch Timer Interrupt Enable Flag
A/D Converter Interrupt Enable Flag
Serial Communication Interrupt Enable Flag
External Interrupt 2 Enable Flag
ADDRESS: 0DB_H
INITIAL VALUE: -000 0000_B
Timer/Counter 1 Interrupt Enable Flag
Timer/Counter 0 Interrupt Enable Flag
External Interrupt 1 Enable Flag
External Interrupt 0 Enable Flag
Watchdog Timer Interrupt Enable Flag
Basic Interval Timer Interrupt Enable Flag
VALUE
0: Disable
1: Enable
Figure 17-3 Interrupt Enable Flag
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FEB. 2005 Ver 1.04