GMS81C7216 Datasheet, PDF (67/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
17.4 External Interrupt
The external interrupt on INT0, INT1 and INT3 pins are edge
triggered depending on the edge selection register IEDS (address
0D8_H) as shown in Figure 17-7.
The edge detection of external interrupt has three transition acti-
vated mode: rising edge, falling edge, and both edge.
INT0 pin
INT1 pin
INT2 pin
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
INT2IF
INT2 INTERRUPT
2 22
IEDS
[0D8_H]
Edge selection
register
Figure 17-7 External Interrupt Block Diagram
INT0 ~ INT2 are multiplexed with general I/O ports (R00~R02).
To use as an external interrupt pin, the bit of Port Mode Register
PMR should be set to “1” correspondingly as shown in Figure 17-
9.
Example: To use as an INT0 and INT2
:
:
;**** Set port as an input port R00,R02
LDM R0DD,#1111_1010B
;
;**** Set port as an external interrupt port
LDM PMR,#05H
;
;**** Set Falling-edge Detection
LDM IEDS,#0001_0001B
:
:
Response Time
The INT0 ~ INT2 edge are latched into INT1IF ~ INT2IF at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be ex-
ecuted. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.
Figure 17-8 shows interrupt response timings.
max. 12 f_XIN period
8 f_XIN period
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 17-8 Interrupt Response Timing Diagram
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