GMS81C7216 Datasheet, PDF (66/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
Example: Register save using push and pop instructions
INTxx: PUSH A
PUSH X
PUSH Y
interrupt processing
POP
Y
POP
X
POP
A
RETI
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop instruc-
tions;
main task
acceptance of
interrupt
interrupt
service task
saving
registers
interrupt return
restoring
registers
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
17-5.
BRK or
TCALL0
B-FLAG
=1
BRK
INTERRUPT
ROUTINE
=0
TCALL0
ROUTINE
RETI
RET
Figure 17-5 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
quests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced.
However, multiple processing through software for special fea-
tures is possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user sets I-
flag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.
Example: During Timer1 interrupt is in progress, INT0 interrupt
serviced without any suspend.
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
A
X
Y
IENH,#08H
IENL,#00H
;Enable INT0 only
;Disable other
;Enable Interrupt
:
:
LDM IENH,#0FFH ;Enable all interrupts
LDM IENL,#0FFH
POP Y
POP X
POP A
RETI
.
Main Program
service
TIMER 1
service
enable INT0
disable other
EI
INT0
service
Occur
TIMER1 interrupt
Occur
INT0
enable INT0
enable other
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Figure 17-6 Execution of Multi Interrupt
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