GMS81C7216 Datasheet, PDF (50/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
Note: The contents of timer data register TDRx should be
initialized with 1_H~FF_H, not to 0_H, because it is not to de-
fined before reset.
In the timer 0, timer register T0 increments from 00_H until it
matches with TDR0 and then reset to 00_H. The match output of
timer 0 generates timer 0 interrupt (latched in T0IF bit)
As TDRx and Tx register are in same address, when reading it as
a Tx, written to TDRx.
In counter function, the counter is increased every 0-to-1 (rising
edge) transition of EC0 or EC2 pin. In order to use counter func-
tion, the bit 3 and bit 4 of the Port mode register PMR are set to
“1” by software. The Timer 0 can be used as a counter by pin EC0
input. Similarly, Timer 2 can be used by pin EC2 input.
TM2
7
6
5
4
3
2
1
0
-
- CAP2 T2CK2 TB2TCCKL1 T2CK0 T2CN T2ST
X
X
0
X
X
X
X
X
ADDRESS: 0E6_H
INITIAL VALUE: 00_H
TM3
- 16BIT1
X
0
EC2 PIN
Edge Detector
T2CK[2:0]
111
SCMR[1:0]
f_XIN
0X
reserved ^1X
÷ 2048
÷ 512
÷ 128
÷ 32
÷8
÷4
÷2
110
101
100
011
010
001
000
MUX
- CAP3 TB3TCCKL1 T3CK0 T3CN T3ST
0
0
X
X
X
X
X means don’t care
ADDRESS: 0E8_H
INITIAL VALUE: 00_H
0
1
T2CN
T2ST
0: Stop
1: Clear and start
T2 (8-bit)
[0E7_H]
clear
Comparator
T2IF
TDR2 (8-bit)
[0E7_H]
TIMER 2
TIMER 2
INTERRUPT
T3CK[1:0]
11
÷8
10
÷ 2 ₀₁
÷ 1 ₀₀
MUX
0
1
T3CN
T3ST
0: Stop
1: Clear and start
T3 (8-bit)
[0EA_H]
clear
Comparator
T3IF
TDR3 (8-bit)
[0E9_H]
TIMER 3
TIMER 3
INTERRUPT
Figure 13-4 8-bit Timer/Counter 2, 3
46
FEB. 2005 Ver 1.04