GMS81C7216 Datasheet, PDF (77/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
19. WATCH / WATCHDOG TIMER
19.1 Watch Timer
The watch timer goes the clock continuously even during the
power saving mode. When MCU is in the Stop or Sleep mode,
MCU can wake up itself every 2Hz or 4Hz or 16Hz.
The watch timer consists of input clock selector, 14-bit binary
counter, interval selector and watch timer mode register WTMR
(address 0EF_H). The WTMR is 5-bit read/write register and
shown in Figure 19-2. WTMR can select the clock input by 2 bits
WTCK[1:0] and interval time selector by 2 bits WTIN[1:0] and
enable/disable bit. The WTEN bit is set to “1” timer start count-
ing. Input clocks can be selected among three different source
which are divided main clock (f_XIN ÷128) or main clock. Recom-
mend the oscillator 4.194304MHz as a main. Because above
main frequency is equal to 128 times of 32.768kHz. Generally
main clock (f_XIN) at WTCK=10_B is not be used, it is just for test
purpose in factory.
In the Stop Mode, the main clock is stopped.
LDM IENL,#XXXX_X1XXB
EI
LDM WTMR,#0100_1000B
WDCK[1:0]
MUX
00 01 10 11
WDCLR
0: Stop
1: Clear and start
2-bit Binary Counter
WTCK[1:0]
reserved ₀₀
f_XIN ÷128 01
f_XIN(test) 10
0
0 _{fW 14-bit Binary Counter}
1
enable
WTEN
overflow
1
enable
When
WDEN
f_XIN = 4.194304 MHz
WDOM
WDTIF
10 01 00
Interval Selector
MUX
WTIN[1:0]
WTIF
to RESET CPU
Watchdog Timer Interrupt
Watch Timer interrupt
Figure 19-1 Block Diagram of Watchdog Timer
19.2 Watchdog Timer
The watchdog timer rapidly detects the CPU malfunction such as
endless looping caused by noise or the like, and resumes the CPU
to the normal state.
The watchdog timer signal for detecting malfunction can be se-
lected either a reset CPU or a interrupt request as you want.
When the watchdog timer is not being used for malfunction de-
tection, it can be used as a timer to generate an interrupt at fixed
intervals.
Watchdog Timer Control
Figure 19-2 shows the watchdog timer control register WDTR
(address 0DF_H). The watchdog timer is automatically enabled
initially and watchdog output to reset CPU but clock input source
is disabled. To enable this function, you should write bit WTEN
of WTMR (address 0EF_H) set to “1”.
The CPU malfunction is detected during setting of the detection
time, selecting of output, and clearing of the binary counter.
Clearing the 2-bit binary counter by bit WDCLR of WDTR is re-
peated within the detection time.
If the malfunction occurs for any cause, the watchdog timer out-
put will become active from the binary counters unless the binary
counter is cleared. At this time, when WDOM=1, a reset is gen-
erated, which drives the RESET pin to low to reset the internal
hardware. When WDOM=0, a watchdog timer interrupt (WD-
TIF) is generated instead of Reset function. This interrupt can be
used general timer as user want.
When main clock is selected as clock input source on the STOP
mode, clock input is stopped so the watchdog timer temporarily
stops counting.
FEB. 2005 Ver 1.04
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