GMS81C7216 Datasheet, PDF(81/121 Page) List of Unclassifed Manufacturers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GMS81C7216 Datasheet, PDF (81/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

◁

GMS81C7208/7216

20.2 STOP Mode

For applications where power consumption is a critical

factor, device provides reduced power of STOP.

Start the Stop Operation

An instruction that STOP causes to be the last instruction

is executed before going into the STOP mode. In the Stop

mode, the on-chip main-frequency oscillator is stopped.

With the clock frozen, all functions are stopped, but the on-

chip RAM and Control registers are held. The port pins

output the values held by their respective port data register,

the port direction registers. The status of peripherals during

Stop mode is shown below.

Peripheral

CPU

RAM

LCD Driver

Basic Interval Timer

Timer/Event Counter

Watch Timer

Main-oscillation

Sub-oscillation

I/O Ports

Control Registers

Release Method

STOP Mode

All CPU operations are disabled

Retain

LCD driver operates continuously

Halted

Halted (Only when the Event counter mode

is enabled, Timer operates normally)

Watch Timer operates continuously

Stop (XIN pin = âLâ, XOUT pin = âLâ)

Oscillation

Retain

RESET, SIO interrupt, Watch Timer inter-

rupt, Timer interrupt (EC0,2), External inter-

rupt

SLEEP Mode

All CPU operations are disabled

Retain

LCD driver operates continuously

BIT operates continuously

Timer/Event Counter operates continuously

Watch Timer operates continuously

Oscillation

Retain

RESET, All interrupts

Table 20-1 Peripheral Operation During Power Down Mode

Note: Since the XIN pin is connected internally to GND to

avoid current leakage due to the crystal oscillator in STOP

mode, do not use STOP instruction when an external clock

is used as the main system clock.

In the Stop mode of operation, VDD can be reduced to minimize

power consumption. Be careful, however, that VDD is not re-

duced before the Stop mode is invoked, and that VDD is restored

to its normal operating level before the Stop mode is terminated.

The reset should not be activated before VDD is restored to its

normal operating level, and must be held active long enough to

allow the oscillator to restart and stabilize.

And after STOP instruction, at least two or more NOP instruction

should be written as shown in example below.

Example)

LDM CKCTLR,#0EBH;32.8ms

;

LDM CKCTLR,#0FBH ;65.5ms

STOP

NOP

The interval timer register CKCTLR should be initialized (0FH or

0EH) by software in order that oscillation stabilization time

should be longer than 20ms before STOP mode.

Release the STOP Mode

The exit from STOP mode is using hardware reset or external in-

terrupt, watch timer, key scan or Timer/Counter.

To release STOP mode, corresponding interrupt should be

enabled before STOP mode.

Specially as a clock source of Timer/Event Counter, EC0 or EC2

pin can release it by Timer/Event Counter interrupt request.

Reset redefines all the control registers but does not change the

on-chip RAM. External interrupts allow both on-chip RAM and

Control registers to retain their values.

Start-up is performed to acquire the time for stabilizing oscilla-

tion. During the start-up, the internal operations are all stopped.

FEB. 2005 Ver 1.04

▷