GMS81C7216 Datasheet, PDF (79/121 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C7208/7216
counter which is free run can not be cleared. The watchdog timer
has 2-bit binary counter. It is incremented by 14-bit binary
counter match as shown in Figure 19-1. Interrupt request flag or
Reset signal are generated by overflow 2-bit binary counter.
During normal operation in the software, 2-bit binary counter
should be cleared by bit WDCLR of WDTR within watchdog
timer overflow.
The time of clearing must be within 3 times of 14-bit binary
counter interval as shown in Figure 19-3.
The worst case, watchdog time is just 3 times of 14-bit counter.
14-bit binary
counter
1FFE 1FFF
1FFE 1FFF
1FFE 1FFF
1FFE 1FFF
012
01 2
012
01 2
2-bit binary
counter
n
0
1
WDTIF interrupt
2
3
0
Counter
Clear
Write WDCLR = 1 at this point
Even if user set to 1 sec.,
worst case 0.75 second
When WDTR = 0011_0111B
Figure 19-3 Watchdog Timer Timing
If the watchdog timer output becomes active, a reset is generated,
which drives the RESET pin low to reset the internal hardware.
The main clock oscillator also turns on when a watchdog timer re-
set is generated in sub clock mode.
FEB. 2005 Ver 1.04
75