M12S64164A Datasheet, PDF (7/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Refresh
Mode Register set
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
Write &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
Burst Stop
Precharge
Bank Selection
All Banks
CKEn-1
CKEn
CS RAS
CAS
WE
DQM
BA0,
BA1
A10/AP
A11,
A9~A0
Note
H
X LL L L X
OP CODE
1,2
H
3
H
LL L H X
X
L
3
L
H
LH H H X
X
3
HX X X X
3
H
X LL H H X V
Row Address
L
Column ₄
H
X LH L H X V
Address
H
(A0~A7) ^4,5
L
Column ₄
H
X LH L L X V
Address
H
(A0~A7) ^4,5
H
X LH H L X
X
6
V
L
H
X LL H L X
X
X
H
HX X X
Clock Suspend or
Entry
H
L
X
LV V V
X
Active Power Down
Exit
L
H XX X X X
HX X X
Entry
H
L
X
LH H H
Precharge Power Down Mode
X
HX X X
Exit
L
H
X
LV V V
DQM
H
X
V
X
7
No Operating Command
HX X X
H
X
X
X
LH H H
Note:
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
1.OP Code : Operating Code
A0~A11 & BA0 ~ BA1: Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4. BA0 ~ BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t_RP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
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