M12S64164A Datasheet, PDF (23/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
12. About Burst Type Control
Basic
MODE
Random
MODE
Sequential Counting
Interleave Counting
Random Column Access
t_CCD = 1 CLK
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
Random
MODE
Interrupt
MODE
1
2
4
8
Full Page
Burst Stop
RAS Interrupt
(Interrupted by
Precharge)
CAS Interrupt
At MRS A210 = “000”
At auto precharge. t_RAS should not be violated.
At MRS A210 = “001”
At auto precharge. t_RAS should not be violated.
At MRS A210 = “010”
At MRS A210 = “011”
At MRS A210 = “111”
At the end of the burst length, burst is warp-around.
t_BDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
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