M12S64164A Datasheet, PDF (30/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
M12S64164A
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CLOCK
CKE
CS
RAS
CAS
tRCD
*Note1
tRC
HIGH
*Note2
ADDR
Ra
Ca0
Rb
Cb0
BA0
BA1
A10/AP
Ra
Rb
CL =2
DQ
CL =3
WE
Qa0 Qa1 Qa2 Qa3
*Note3
Qa0 Qa1 Qa2 Qa3
*Note3
Qb0 Qb1 Qb2 Qb3
tRDL
Qb0 Qb1 Qb2 Qb3
tRDL
DQM
Row Active
( A - Bank )
Read
( A - Bank )
Precharge
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
:Don't Care
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (t_SHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
30/45