M12S64164A Datasheet, PDF (26/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
FUNCTION TRUTH TABLE (TABLE2)
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
( n-1 )
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
L
L
CKE
n
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
CS RAS CAS WE
XX X X
HX X X
LH H H
LH H L
LH L X
LL XX
XX X X
XX X X
HX X X
LH H H
LH H L
LH L X
LL XX
XX X X
XX X X
HX X X
LH H H
LH H L
LH L X
LL HH
LL HH
LL L H
LL L L
XX X X
XX X X
XX X X
XX X X
XX X X
ADDR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
X
OP Code
X
X
X
X
X
ACTION
INVALID
Exit Self Refresh Æ Idle after t_RFC (ABI)
Exit Self Refresh Æ Idle after t_RFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh Æ ABI
Exit Self Refresh Æ ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
NOP
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
Note
6
6
7
7
8
8
8
9
9
Abbreviations: ABI = All Banks Idle, RA = Row Address
*Note:
6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + t_SS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
26/45