M12S64164A Datasheet, PDF (15/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Self refresh entry command
( CS , RAS , CAS , CKE = Low, WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the device exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
M12S64164A
Burst stop command
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
( CS = Low, RAS , CAS , WE = High)
This command is not a execution command. No operations begin or terminate by
this command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
15/45