M12S64164A Datasheet, PDF (35/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Read & Write cycle with Auto Precharge @ Burst Length = 4
M12S64164A
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
Ra
Rb Ca
Cb
BA0
BA1
A10/AP
Ra
Rb
CL =2
DQ
CL =3
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
DDb0 Ddb1 DDb2 DDd3
WE
DQM
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Row Active
( D - Bank )
Auto Precharge
Start Point
W rite with
Auto Precharge
(D-Bank)
Auto Precharge
Start Point
(D-Bank)
:Don't Care
*Note: 1. t_CDL should be controlled to meet minimum t_RAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
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