M12S64164A Datasheet, PDF (38/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
CLOCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15 16
17
18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
tBDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
tRDL
*Note1
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
W rite
(A-Bank)
Precharge
(A-Bank)
:Don't Care
*Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of t_RDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
38/45