M12S64164A Datasheet, PDF (6/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
PARAMATER
-6
SYMBOL
MIN MAX
-7
MIN MAX
CLK cycle time
CAS latency = 3
tCC
CAS latency = 2
6
7
1000
1000
10
10
CLK to valid
CAS latency = 3
5.5
6
output delay
tSAC
CAS latency = 2
6
6
Output data
CAS latency = 3
2.5
2.5
hold time
tOH
CAS latency = 2
2.5
2.5
CLK high pulse width
tCH
2.5
2.5
CLK low pulse width
tCL
2.5
2.5
Input setup time
tSS
1.5
1.5
Input hold time
tSH
1
1
CLK to output in Low-Z
tSLZ
0
0
CLK to output
CAS latency = 3
5.5
6
in Hi-Z
tSHZ
CAS latency = 2
6
6
-10
MIN MAX
10
1000
12
7
8
2.5
2.5
3
3
2.5
1.5
0
7
8
UNIT NOTE
ns
1
ns
1,2
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
-
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
6/45