M12S64164A Datasheet, PDF (14/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Write command
( CS , CAS , WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
M12S64164A
Read command
( CS , CAS = Low, RAS , WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
( CS , RAS , CAS = Low, WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
During t_RFC period (from refresh command to refresh or activate command), the
device cannot accept any other command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
14/45