M12S64164A Datasheet, PDF (5/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
AC OPERATING TEST CONDITIONS (VDD = 2.5V ± 0.2V ，T_A = 0 to 70 °C )
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
VALUE
0.9*V_DDQ/0.2
0.5*V_DDQ
tr/tf = 1/1
0.5*V_DDQ
See Fig. 2
M12S64164A
UNIT
V
V
ns
V
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
Row active to row active delay
t_RRD(min)
RAS to CAS delay
t_RCD(min)
Row precharge time
t_RP(min)
Row active time
t_RAS(min)
t_RAS(max)
Row cycle time
@ Operating
@ Auto refresh
t_RC(min)
t_RFC(min)
Last data in to col. address delay
t_CDL(min)
Last data in to row precharge
t_RDL(min)
Last data in to burst stop
t_BDL(min)
Col. address to col. address delay t_CCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
VERSION
-6
-7
-10
12
14
20
18
20
30
18
20
30
40
42
60
100
58
63
90
60
70
100
1
2
1
1
2
1
UNIT
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ea
NOTE
1
1
1
1
1
1,5
2
2
2
3
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t_RFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
5/45