M12S64164A Datasheet, PDF (32/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
Page Read Cycle at Different Bank @ Burst Length = 4
CLOCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15
16 17 18 19
CKE
CS
*Note1
HIGH
RAS
CAS
*Note2
ADDR
BA0
RAa
RBb CAa
RCc CBb
RDd CCc
CDd
BA1
A10/AP
CL=2
DQ
CL=3
RAa
RBb
WE
RCc
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQM
Row Active
( A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
:Don't Care
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
32/45