M12S64164A Datasheet, PDF (34/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
M12S64164A
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
BA0
CAa
RDb
CDb RBc
CBc
BA1
A10/AP
RAa
CL =2
DQ
CL =3
RBb
QAa0 QAa1 QAa2 QAa3
RAc
tCDL ^*Note1
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1 QBc2
QAa0 QAa1 QAa2 QAa3
DDb0 Ddb1 DDb2 DDd3
QBc0 QBc1
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
W rite
(D-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
:Don't Care
*Note: 1. t_CDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
34/45