M12S64164A Datasheet, PDF (24/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS RAS CAS WE BA
ADDR
ACTION
HXXX
X
X
NOP
L HHH
X
X
NOP
L HH L
X
X
ILLEGAL
LHLX
BA CA, A10/AP ILLEGAL
L LHH
BA
RA
Row (&Bank) Active ; Latch RA
L LHL
BA
A10/AP NOP
L
L
L
H
X
X
Auto Refresh or Self Refresh
L
L
L
L OP code OP code Mode Register Access
HXXX
X
X
NOP
L HHH
X
X
NOP
L HH L
X
X
ILLEGAL
LHLH
BA CA, A10/AP Begin Read ; latch CA ; determine AP
L
H
L
L
BA CA, A10/AP Begin Write ; latch CA ; determine AP
L LHH
BA
RA
ILLEGAL
L LHL
BA
A10/AP Precharge
L
L
L
X
X
HXXX
X
L HHH
X
L HH L
X
X
ILLEGAL
X
NOP (Continue Burst to End Æ Row Active)
X
NOP (Continue Burst to End Æ Row Active)
X
Term burst Æ Row active
LHLH
BA CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA CA, A10/AP Term burst, New Write, Determine AP
L LHH
BA
RA
ILLEGAL
L LHL
BA
A10/AP Term burst, Precharge timing for Reads
L
L
L
X
X
HXXX
X
L HHH
X
L HH L
X
X
ILLEGAL
X
NOP (Continue Burst to End Æ Row Active)
X
NOP (Continue Burst to End Æ Row Active)
X
Term burst Æ Row active
LHLH
BA CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA CA, A10/AP Term burst, New Write, Determine AP
L LHH
BA
RA
ILLEGAL
L LHL
BA
A10/AP Term burst, Precharge timing for Writes
L
L
L
X
X
X
ILLEGAL
HXXX
X
L HHH
X
X
NOP (Continue Burst to End Æ Row Active)
X
NOP (Continue Burst to End Æ Row Active)
L HH L
X
X
ILLEGAL
LHLX
BA CA, A10/AP ILLEGAL
L LHX
BA
RA, RA10 ILLEGAL
L
L
L
X
X
X
ILLEGAL
HXXX
X
X
NOP (Continue Burst to End Æ Row Active)
L HHH
X
X
NOP (Continue Burst to End Æ Row Active)
L HH L
X
X
ILLEGAL
LHLX
BA CA, A10/AP ILLEGAL
L LHX
BA
RA, RA10 ILLEGAL
L
L
L
X
X
X
ILLEGAL
Note
2
2
4
5
5
2
2
3
2
3
3
2
3
2
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
24/45