M12S64164A Datasheet, PDF (13/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
COMMANDS
Mode register set command
( CS , RAS , CAS , WE = Low)
The device has a mode register that defines how the device operates. In this
command, A0 through A11 and BA0~BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state. During 2CLK
following this command, the device cannot accept any other commands.
M12S64164A
Activate command
( CS , RAS = Low, CAS , WE = High)
The device has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A11.
This command corresponds to a conventional DRAM’s RAS falling.
Precharge command
( CS , RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the device can’t accept the activate command to the
precharging bank during t_RP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
13/45