M12S64164A Datasheet, PDF (39/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
17 18
19
CLOCK
CKE
tSS
*Note1
*Note2
tSS
tSS
*Note3
CS
RAS
CAS
ADDR
BA0
Ra
Ca
BA1
A10/AP
DQ
Ra
tSHZ
Qa0 Qa1 Qa2
WE
DQM
Precharge
Power-Down
Entry
Row Active
Precharge
Power-Down
Exit
Active
Power-down
Entry
Read
Active
Power-down
Exit
Precharge
: Don't care
*Note: 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + t_SS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
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