M12S64164A Datasheet, PDF (33/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Page Write Cycle at Different Bank @ Burst Length = 4
M12S64164A
CLOCK
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14
15 16 17 18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
BA0
BA1
RBb CAa
CBb RCc
RDd CCc
CDd
*Note2
A10/AP
DQ
RAa
WE
DQM
RBb
RCc
RDd
DAa0 _{DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0} DCc1 _DDd0DDd1 CDd2
tCDL
tRDL
*Note1
Row Active
( A - Bank )
Write
(A-Bank)
Row Active
(B-Bank)
W r ite
(B-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Row Active
(C-Bank)
W ri te
(C-Bank)
Precharge
(All Banks)
: Don't care
*Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
33/45