M12S64164A Datasheet, PDF (21/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
8. Burst Stop & Interrupted by Precharge
CLK
1) W ri te B ur st S top ( BL= 8 )
CMD
WR
ST OP
DQ M
DQ
D0 D1 D2 D3 D4 _D5
t B DL ^{*N ote1}
M12S64164A
CLK
CM D
DQ M
1) W ri te in terr up ted by pr echa rg e ( BL= 4)
WR
t R DL
* N ote3
PRE
* N ote4
DQ
D0 D1 Mask Mask
CL K
2 )R e ad Bur st St op (B L= 4)
CMD
DQ (CL2)
D Q( C L3)
RD
STO P
* N ote2
Q0 Q1
*Note 2
Q0 Q1
2 )R ea d i nter ru pted by pr echar ge (BL =4)
CL K
CMD
RD
*N ote5
PRE
D Q( C L2)
DQ( CL3)
Q0 Q1 Q2 _Q3
Q0 Q1 Q2 ^Q3
9. MRS
1)M od e R eg is te r S et
CLK
CMD
*N ot e6
PRE
t RP
MRS
ACT
2C LK
*Note:
1. t_BDL: 1 CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
3. Write burst is terminated. t_RDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying t_RAS min delay) with DQM.
6. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
21/45