M12S64164A Datasheet, PDF (4/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12S64164A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T_A = 0 to 70 °C
PARAMETER
SYMBOL
TEST CONDITION
Operating Current
(One Bank Active)
I_CC1
Precharge Standby Current ^ICC2P
in power-down mode
I_CC2PS
Precharge Standby Current
in non power-down mode
I_CC2N
I_CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
I_CC3P
I_CC3PS
I_CC3N
I_CC3NS
Operating Current
(Burst Mode)
I_CC4
Refresh Current
I_CC5
Self Refresh Current
I_CC6
Burst Length = 1, t_RC ≥ t_RC(min), I_OL = 0 mA,
tcc = tcc(min)
CKE ≤ V_IL(max), tcc = tcc(min)
CKE & CLK ≤ V_IL(max), tcc = ∞
CKE ≥ V_IH(min), CS ≥ V_IH(min), tcc = tcc(min)
Input signals are changed one time during 2CLK
CKE ≥ V_IH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
CKE ≤ V_IL(max), tcc = tcc(min)
CKE & CLK ≤ V_IL(max), tcc = ∞
CS CKE ≥ V_IH(min), CS ≥ V_IH(min), tcc = 15ns
Input signals are changed one time during 2 CLKs
All other pins ≥ VDD - 0.2V or ≤ 0.2V
CKE ≥ V_IH(min), CLK ≤ V_IL(max), tcc = ∞
input signals are stable
IOL = 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
t_RFC ≥ t_RFC(min), tCC = tcc(min)
CKE ≤ 0.2V
VERSION
-6 -7 -10
85 85 60
2
1
20
10
10
10
30
25
150 140 120
150 140 120
1
UNIT NOTE
mA
1,2
mA
mA
mA
mA
mA
mA 1,2
mA
mA
Note: 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
4/45