MA31750 Datasheet, PDF (9/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
disabled when operating with devices which do not support
parity generation by asserting the DPARN (Disable Parity)
input low. The checking polarity (odd or even) is selectable
with Configuration Register bit 6.
3.5. TIMER OPERATIONS
The MA31750 implements interval timers A and B, a
trigger-go counter, and a bus fault timer. A discussion of each
follows:
3.5.1. TIMERS A AND B
Two general-purpose, 16-bit timers are provided in the
processor. Timer A is clocked by the TCLK input; timer B is
clocked by an internally generated TCLK/10. The divider
circuit is reset when Timer B is reset to give deterministic
processor operation. MIL-STD-1750 requires TCLK to be a
100kHz pulse train. If allowed to overflow, timers A and B will
set level 7 and level 9 interrupt requests respectively. Each
timer can be read, loaded, started and stopped by using XIO
commands as identified in figure 20c.
Each timer has associated with it a reset register from
which the timer is automatically loaded following a software
reset or overflow. These registers are initially loaded with zero
but may be reloaded from software (using the XIO instructions
OTA and OTB) to provide greater control over the count
period.
The MA31750 timers A and B will be disabled when the
device enters Console mode, as required by MIL-STD-1750A
Notice 1.
3.6. CONSOLE OPERATION
The MA31750 is capable of interfacing directly to an
external console, allowing the developer to: examine and
change the contents of internal registers, memory and IO
devices; single step code and halt the processor. Applications
Note 3 provides a full description of the Console interface, its
implementation and operation.
3.7. MULTIPROCESSOR SUPPORT
Once initialisation has been completed, the processor will
begin instruction execution by executing a sequence of micro-
instructions, each one machine cycle (two system clock
periods) long. Each machine cycle may perform either an
internal or an external operation; if the operation is purely
internal then the system busses will not be in use and may be
reassigned to another processor.
An external machine cycle (indicated by REQN low during
the second half of the previous cycle) will cause the processor
to stall upon completion of the current microcycle, awaiting
GRANTN asserted low. Whilst GRANTN is high the busses
remain undriven.
In simple, single processor systems which use no DMA
devices the GRANTN line should be tied to GND to allow the
processor to retain control of the busses. The LOCKN and
REQN pins can be left open-circuit in this case. Applications
Note 11 provides further information for designers of systems
with more than one bus master.
4. SOFTWARE CONSIDERATIONS
3.5.2. TRIGGER-GO COUNTER
This 16-bit counter is clocked by the TCLK input and is
typically used as a system “watchdog” timer. It is enabled
during system initialisation and may be preset under software
control to give a wide range of timeout intervals. In order that
the count period may be controlled, a reset register is
provided. On reset, this register is loaded with zero, but can be
reloaded under software control to take any value between 0
and FFFF₁₆ (a value of zero gives the maximum count period).
This allows the timeout period to be varied between 20us and
0.65s. Note that there is no value which disables the timer.
The counter is incremented on each TCLK falling edge.
Whenever the trigger-go counter overflows, TGON drops low
and remains low until the counter is reloaded from the reset
register via the GO internal XIO command. TGON low would
typically be used to initiate a user-defined system recovery
action such as a system reset.
3.5.3. BUS FAULT TIMER
All bus operations are monitored to ensure timely
completion. A hardware timeout circuit is enabled at the start of
each memory and l/O transfer (DSN high-to-low transition) and
is reset upon receipt of the external ready (RDYN) signal. If
this circuit fails to reset within a minimum of one TCLK period
or a maximum of two TCLK periods, either bit 8 (if the
transaction is with memory) or bit 5 (if the transaction is with l/
O) of the Fault Register (FT) is set. This sets Pending Interrupt
level 1 and causes the strobes to be suppressed and the
current bus cycle to be aborted. The MIL-STD-1750 instruction
is aborted, and control passes to the level 1 interrupt service
routine (if the level 1 interrupt is unmasked). The timeout
mechanism is disabled and reset if DTON is asserted low.
4.1. OPERATING MODES
The MA31750 is capable of being operated in one of two
basic modes as previously mentioned. These are described in
detail below:
4.1.1 1750A MODE
1750A mode is a full implementation of MIL-STD-1750A
(Notice 1) and includes some of the optional features
mentioned in this standard.
4.1.2 1750B MODE
1750B mode is an implementation of the proposed MIL-
STD-1750B, Option 2, Draft of 17th July 1988. This mode
extends the basic 1750A mode operation. Note that the
transcendental functions SIN, COS, LN etc. (Option 3 of MIL-
STD-1750B) are not supported. Features new to MIL-STD-
1750B which are in violation of MIL-STD-1750A are only
enabled in 1750B mode. The additional instructions available
in 1750B mode are detailed in figure 20b.
4.2. ACCESSING IO USING XIO AND VIO COMMANDS
MIL-STD-1750 defines a 64KWord addressing space
which is available exclusively for accessing IO resources. Two
special commands, XIO and VIO, are provided as part of the
instruction set for accessing this space. Port addresses are
specified as a 16-bit Command word which is supplied as a
parameter to the XIO/VIO instruction. The MSB of the
Command word indicates the direction of data transfer
between the port and the register specified in the XIO
command (a 1 in the MSB indicates that the port is being read,
whilst 0 indicates a write to the port).
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