MA31750 Datasheet, PDF (34/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
P in Na me Func t ion
Description
POWER
VDD
GND
Power Supply
Ground
DC power supply input - nominally +5V.
0V reference point.
CLOCK SI GNALS
CLK
System Clock
CLKOUT Clock Out
TCLK
Timer Clock
100kHz sq. wave
Schmitt Input clock signal.
For correct operation of the timers the CLK frequency should be at least 9 times that of
TCLK.
Buffered reference clock derived directly from the internal clock. This signal is used to
reference all of the external strobes and internal timing events and may be used to
synchronise an external system to the processor.
This Schmitt input clock is used by the internal 16-bit timers A and B and by the Trigger-Go-
counter. MlL-STD-1750 requires this signal to have a frequency of 100kHz.
SYSTEM BUSES
A00-A15 Address bus
A00 is MSB
D00-D16 Data bus
D00 is MSB
An active-high address bus which is input during bus cycles not assigned to this CPU. A00
is the most significant bit.
An active-high data bus which is tristate during bus cycles not assigned to this CPU. D00 is
the most significant bit. D16 is the optional parity check bit.
BUS CONTROL
AS
Address Strobe This active-high bidirectional signal establishes the beginning and end of each bus cycle.
Active HIGH
The trailing edge (high to low transition) is used to sample bus cycle-related faults into the
fault register. The leading edge guarantees that a valid address is on the address bus.
During cycles not assigned to this CPU the AS line is an input to allow the falling edge to
continue to latch bus cycle related faults into the fault register.
DSN
Data Strobe
This active-low signal indicates the presence of data on the system data bus. During a read
Active LOW
cycle DSN goes low to indicate that the processor is requesting data from the bus, whilst in
a write cycle DSN indicates that data is present on the bus. This signal is tristate in bus
cycles not assigned to this CPU.
M/ION
Memory/IO Select This signal indicates whether the current bus cycle is accessing memory (high) or IO (low)
Memory=HIGH addressing space. This signal becomes valid shortly after the start of a machine cycle and
IO=LOW
remains valid throughout. M/ION becomes an input on cycles not assigned to the CPU to
ensure that faults are latched into the correct bit of the fault register.
RD/WN
Read/Write
This signal indicates the direction of data transfer on the system data bus. Data is read in
Select.
by the processor when high, and written out when low. This signal becomes valid shortly
Read=HIGH
after the start of a machine cycle and remains valid throughout. RD/WN is tristate during
Write=LOW
cycles not assigned to this CPU.
O/IN
Operand/Instruct This signal indicates whether the current bus cycle is accessing operand (high) or
Select.
instruction (low) addressing space. This signal becomes valid shortly after the start of a
Operand=HIGH machine cycle and remains valid throughout. O/IN is an input during cycles not assigned to
Instr.=LOW
this CPU, to ensure correct operation of the MFPR and the MFAR.
RDN
Read Strobe.
This active-low output is asserted low with DSN during read cycles. It is driven high on the
Active LOW
same clock edge as that used by the processor to latch the input data. This signal is
tristate in bus cycles not assigned to this CPU.
WRN
Write Strobe.
This active-low output signal is asserted low with DSN during write cycles. The rising edge
Active LOW
should be used by the system to latch data from the data bus. This signal is tristate in bus
cycles not assigned to this CPU.
RDYN
Ready.
This input signal allows the basic machine cycle of the processor to be extended to
Active LOW
accommodate slower peripheral or memory devices. Ready may be asserted high to add an
integer number of CLK cycles (wait states) to the machine cycle. The line must be asserted
low to allow processing to proceed. RDYN has no effect on cycles dedicated to internal
operations.
Not e : If RDYN is held high during two consecutive TCLK high-to-low transitions (with DSN
low), a bus timeout fault will occur and will be indicated in the appropriate bit in the fault
register. The occurrence of this fault will cause the state sequencer to terminate the
current machine cycle and begin the next. At the end of the current macro-instruction
execution will branch, unless masked, to the machine error interrupt (level 1) software
routine. The DTON signal may be used to override this feature.
Figure 39: Pin Descriptions
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