MA31750 Datasheet, PDF (30/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
No. Parameter
1
ADDRESS valid to AS rising
2
ADDRESS valid after AS falling
3
CLKOUT low to ADDRESS valid
4
CLKOUT rising to AS rising
5
CLKOUT falling to AS falling
6
Data setup to RDN rising
7
Data hold after RDN rising
8
CLKOUT falling to DSN, RDN, WRN falling
9
CLKOUT falling to DSN, RDN, WRN rising
10 RDYN setup to CLKOUT falling
11 RDYN hold after CLKOUT falling
12 WRN falling to write data valid
13 Write data valid after WRN rising (Test Load 2)
14 DSN falling to data bus driven (write) (Test Load 2)
15 DSN rising to data bus hi-Z (write) (Test Load 2)
16 CLKOUT falling to REQN falling
17 CLKOUT falling to REQN rising
18 GRANTN setup to CLKOUT falling
19 GRANTN hold after CLKOUT falling
20 CLKOUT falling to control, strobes and busses hi-Z (GRANTN removed) (Test Load 2)
21 CLKOUT falling to control, strobes and busses hi-Z (GRANTN removed) (Test Load 2)
22 AS falling to control, strobes and busses hi-Z (GRANTN removed) (Test Load 2)
23 GRANTN falling to control, strobes and busses driven
24 GRANTN rising to control, strobes and busses undriven (RESETN = LOW)
25 CLKOUT falling to INTAKN changing
26 CLKOUT falling to LOCKN valid
27 RESETN low pulse width
28 RESETN low to strobes inactive (GRANTN = LOW)
29 RESETN high to strobes valid (GRANTN = LOW)
30 RESETN falling to DMAE, NPU low, SUREN high
31 RESETN rising to DMAE, SUREN, NPU initialized
32 RESETN rising to first bus cycle (configuration word read)
33 RESETN rising to CONFWN low
34 RESETN rising to first instruction fetch
35 Interrupt setup to CLKOUT rising (level sensitive)
36 Interrupt hold after CLKOUT rising (level sensitive)
37 Interrupt pulse width (edge-sensitive)
38 MPROEN/EXADEN/PEN setup to AS falling (MPROEN and EXADEN sampled on early time-out)
39 MPROEN/EXADEN/PEN hold after AS falling (MPROEN and EXADEN sampled on early time-out)
40 CLKOUT falling to CONFWN changing
41 CLKOUT falling to DISCON changing
42 DPARN setup to CLKOUT falling
43 DPARN hold after CLKOUT falling
44 TCLK falling to TGON low
45 CONREQN hold after Console Command Chip Selection
46 CLKOUT falling to SNEW rising
47 CLKOUT falling to SNEW falling
48 CLKOUT falling to SUREN/DMAE valid
49 CLKOUT falling to SUREN/DMAE invalid
50 MPROEN/EXADEN setup to CLKOUT falling (to insert early wait states)
51 MPROEN/EXADEN hold after CLKOUT falling (to insert early wait states)
52 CLKOUT falling to TGON rising (following XIO GO)
53 AS low pulse width
54 AS falling to BUSFAULTN valid
55 CLK rising to CLKOUT rising
56 CLK falling to CLKOUT falling
57 MION valid to AS rising
58 MION valid after AS falling
59 OIN/RDWN valid to AS rising
60 OIN/RDWN valid after AS falling
61 SYSFN/FLT7N setup to CLKOUT (at end of cycle)
62 CLKOUT falling to NPU changing
63 DTON setup to TCLK falling
64 DTON hold after TCLK falling
† This timing includes MA31751 Setup Cycles and Built In Test Cycles.
Mil-Std-883, Method 5005, Subgroups 9, 10, 11.
TL = Low CLK period (ns), TH = High CLK period (ns).
Test Conditions: Vdd = 5.0V ±10%, Temperature = -55^oC to 125^oC, Vil = 0.0V, Vih = Vdd.
Output loads: All test load 1 unless otherwise specified.
Output Threshold: 50% Vdd (Load 1), Vss+1V, Vdd-1V (Load 2).
Figure 32a: Timing Parameters for MA31750
Min.
TL-25
5
-
-
-
15
0
-5
-5
25
0
5
5
5
-
15
8
15
0
2
10
4
4
10
4
4
10
10
4
-
28
6
7
T31+16
15
20
10
5
15
2
8
10
5
5
-
4
4
4
4
40
0
20
0.5T-5
-
5
5
TL-20
1
TL-20
1
10
-
10
10
Max.
-
25
40
20
15
-
-
10
10
-
-
35
40
35
40
55
40
-
-
25
50
40
25
50
30
35
-
55
30
50
13960†
6
7
T31+16
-
-
-
-
-
25
45
-
-
45
3
30
30
30
30
-
-
80
0.5T+10
45
25
25
-
25
-
25
-
30
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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