MA31750 Datasheet, PDF (15/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

5.3. INSTRUCTION SUMMARY
OPERATION
SINGLE LOAD/STORE
Single Precision Load
Double-Precision Load
Single-Precision Store
Store Non-Negative Constant
Double-Precision Store
Load Multiple Registers
Store Multiple Registers
COMPARE
Single-Precision Compare
Compare Between Limits
Double-Precision Compare
BYTE
Load From Upper Byte
Load From Lower Byte
Store Into Upper Byte
Store Into Lower Byte
Exchange Bytes in Register
MA31750
Mnem.
Format
Opcode Memory Internal
(Ext)
cycles
Cycles
LR
R
81
1
0
LB
B
0X
2
1
LBX
BX
4X 0
2
1
LISP
ISP
82
1
0
LISN
ISN
83
1
0
L
D,DX
80
3
0
LIM
IM,IMX
85
2
0
LI
I,IX
84
4
0
DLR
R
87
1
0
DLB
B
0X
3
1
DLBX
BX
4X 1
3
1
DL
D,DX
86
4
0
DLI
I,IX
88
5
0
STB
B
0X
2
0
STBX
BX
4X 2
2
1
ST
D,DX
90
3
0
STI
I,IX
94
4
0
STC
D,DX
91
3
0
STCI
I,IX
92
4
0
DSTB
B
0X
3
0
DSTX
BX
4X 3
3
1
DST
D,DX
96
4
0
DSTI
I,IX
98
5
0
LM
D,DX
89
3+n
0
STM
D,DX
99
2+n
1
CR
R
F1
1
CB
B
3X
2
CBX
BX
4X C
2
CISP
ISP
F2
1
CISN
ISN
F3
1
C
D,DX
F0
3
CIM
IM
4A A
2
CBL
D,DX
F4
4
DCR
R
F7
1
DC
D,DX
F6
4
0
1
1
1
0
0
0
2.7a
0
0
LUB
D,DX
8B
3
1
LUBI
I,IX
8D
4
1
LLB
D,DX
8C
3
0
LLBI
I,IX
8E
4
0
STUB
D,DX
9B
4
0
SUBI
I,IX
9D
5
0
STLB
D,DX
9C
4
1
SLBI
I,IX
9E
5
1
XBR
S
EC
1
0
Figure 20a: Instruction Summary
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