MA31750 Datasheet, PDF (14/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
5. PERFORMANCE
5.1. BENCHMARKING
Figure 20a defines the number and type of machine cycles
associated with each MIL-STD-1750 instruction. This
information may be used when benchmarking MA31750
performance. The Digital Avionics Instruction Set (DAIS) mix,
which defines a typical frequency of occurrence for MIL-STD-
1750A instructions, is used here for this purpose.
One problem with the DAIS mix is that it does not reflect the
impact of data dependencies on system performance. E.g. a
multiplication in which the operand is zero may be performed
much faster than one with two non-zero operands.
Realistic benchmarks must therefore take both the
instruction mix and data dependencies into account. To this
end, machine cycle counts in figure 20a which have data
dependencies are annotated with either an “a” or “wa” suffix.
An “a” suffix reflects an average number of machine cycles
(where each of several possibilities is equally likely) and a “wa”
suffix reflects a weighted average number of machine cycles
(where some data possibilities are more likely than others).
Weighted averages are only applicable to floating-point
operations. Normalisation and alignment operations are also
represented. Figure 19 shows MA31750 throughput, at
various frequencies and wait states, for the floating point DAIS
mix.
5.2. EXPANDED MEMORY PERFORMANCE
The inclusion of an MMU (Memory Management Unit) will
degrade the throughput performance of the processor in two
ways. Firstly, each memory access will have an additional
overhead associated with the formation of the extended
address from the MMU. This may require that the processor
inserts wait states to lengthen each external cycle. Secondly,
the MMU itself may require that some ‘housekeeping’ work be
done by the processor, which will lengthen the program
execution time. There are no widely accepted benchmarks
which may be used to measure the resultant decrease in
throughput.
3.5
3
2.5
2
1.5
1
0.5
0
0
25MHz
20MHz
15MHz
10MHz
5MHz
1
2
3
4
Waitstates
Figure 19: Throughput (MIPS) with Waitstates
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