MA31750 Datasheet, PDF (19/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
OPERATION
Mnem.
Format
Opcode
(Ext)
CONVERT
Convert Floating-Point to 16-Bit FIX
R
E8
Integer
Convert 16-Bit Integer to
FLT
R
E9
Floating-Point
Convert Extended-Precision
EFIX
R
EA
Floating-Point to 32-Bit Integer
Convert 32-Bit Integer to
EFLT
R
EB
Extended-Precision Floating-
Point
SHIFT
Shift Left Logical
SLL
R
60
Shift Right Logical
SRL
R
61
Shift Right Arithmetic
SRA
R
62
Shift Left Cyclic
SLC
R
63
Double Shift Left Logical
DSLL
R
65
Double Shift Right Logical
DSRL
R
66
Double Shift Right Arithmetic
DSRA
R
67
Double Shift Left Cyclic
DSLC
R
68
Shift Logical, Count in Register SLR
R
6A
Shift Arithmetic, Count in
SAR
R
6B
Register
Shift Cyclic, Count in Register SCR
R
6C
Double Shift Logical, Count in DSLR
R
6D
Register
Double Shift Arithmetic, Count in DSAR
R
6E
Register
Double Shift Cyclic, Count in
DSCR
R
6F
Register
I/O (See I/O Command
Summary)
Execute I/O
Vectored I/O (n transfers)
XIO**
VIO**
IM,IMX
48
D,DX
49
SPECIAL
Move Multiple Words, Memory-
to-memory (n-words moved)
Exchange Words in Registers
Load Status
No Operation
Break Point
MOV
XWR
LST**
LSTI**
NOP
BPT
S
R
D,DX
I,IX
S
S
93
ED
7D
7C
FF 00
FF FF
Figure 20a (continued): Instruction Summary
Memory
cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
***
1+2n
1
6
7
1
1
Internal
Cycles
7.1a
3
8.5a
9
0
0
0
0
0
0
0
0
2
5a
2
2
5
2
4.3a
***
7
2
1
1
2
6
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