MA31750 Datasheet, PDF (8/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
Interrupt LP
SP
No.
Address Address
PWRD
0
20
21
ME
1
22
23
INT02
2
24
25
FI.P o/f
3
26
27
Fx.P o/f
4
28
29
BEX
5
2A
2B
FI.P u/f
6
2C
2D
Timer A
7
2E
2F
INT08
8
30
31
Timer B
9
32
33
INT10
10
34
35
INT11
11
36
37
IOI1
12
38
39
INT13
13
3A
3B
IOI2
14
3C
3D
INT15
15
3E
3F
Note: Addresses (in hex) are in operand space
Figure 12: Interrupt Pointer Address
When an interrupt request is latched into Pl, it is ANDed
with its corresponding mask bit in the mask register (MK).
NOTE: Interrupt level 0 is non-maskable. Any unmasked
pending interrupts are output to the priority encoder where the
highest priority is encoded as a 4-bit vector. If interrupts are
enabled and an unmasked interrupt is pending, the priority
encoder will assert an interrupt request to the sequencer. 1 or
2 extra CLKs will be inserted into the machine cycle on which
the interrupt request is asserted.
Upon completing execution of each MIL-STD-1750A or B
instruction, the sequencer checks the state of the priority
encoder interrupt request. If a request is asserted, the
sequencer branches to the microcode interrupt service
routine. This routine reads the 4-bit pending interrupt vector
and then uses this value to calculate the appropriate interrupt
linkage (old processor context save area) and service (new
context load area) pointers. Figure 11 depicts this relationship.
Figure 12 defines the pointer values.
Using the linkage and service pointers, the microcode
interrupt service routine performs the following: (1) the current
contents of the status word, mask register, and instruction
counter are saved; (2) a write status word (WSW) I/O
command is executed with an all zero data word; (3) the new
mask is loaded into MK and interrupts are disabled; (4) the
new status word is read and checked for a valid Address State
(AS[0:3]) field - If the address state is non-zero and an MMU is
not present, AS[0:3] is set to zero and fault 11 (address state
error) is set in the fault register FT); (5) a write status word
command using the new status word is performed; and (6) the
new IC value is loaded into IC, the instruction pipeline is
flushed and refilled starting at the new address, and instruction
execution begins.
[NOTE: The steps listed above represent a summary of
actions performed during interrupt servicing and do not
necessarily reflect the actual order in which these events take
place.]
If an address state fault occurs during the service routine,
interrupt level 1 will be set. This interrupt will be serviced when
interrupts are re-enabled unless it is masked by the new value
in MK.
3.4.8. FAULT SERVICING
Five user fault inputs are provided. A low on any of the
three bus-cycle-related fault inputs, EXADEN, MPROEN or
PEN, will be latched into the Fault Register (FT) on the next
falling edge of AS. A low on either of the two general purpose
fault inputs, FLT7N or SYSFN, will be latched immediately and
will be sampled into the appropriate bit of FT on the falling
edge of AS.
Any fault which sets a bit in the FT immediately causes a
level 1 pending interrupt to be entered into the PI register. This
interrupt is maskable but may not be disabled.
This interrupt will be serviced at the end of the currently
executing 1750 instruction if not masked. The microcoded
interrupt service routine reads the interrupt priority vector and
clears the bit relating to the serviced interrupt from the PI.
However, the FT retains the set fault bits until the FT is cleared
using the XIO RCFR command. (A non-destructive read of the
FT is provided by the XIO RFR command.) Anti-repeat logic
between the FT and the PI prevents the same fault being
latched and serviced twice. However, as all FT bits are ORed
together and input to PI bit 1, this also prevents any other faults
being serviced until the fault register has been cleared. It is
imperative, therefore, that the fault service routine executes a
RCFR XIO before exiting. Different types of faults are serviced
slightly differently as follows:
3.4.8.1. MPROEN and EXADEN
If MPROEN and/or EXADEN are low on a falling clock
edge with AS and DSN high (see figure 23a), the processor will
wait in this state. If either fault input remains low during two
falling edges of TCLK, the cycle is forced to complete but RDN/
WRN and DSN are inhibited (see figure 24b). This allows the
processor to prevent erroneous accesses. An access fault will
be registered as AS falls at the end of the cycle.
3.4.8.2. PEN
External parity errors are latched into the FT on the falling
edge of AS. The fault bit set is dependant upon the type of
transfer taking place (memory, IO or DMA).
3.4.8.3. FLT7N and SYSFN
These faults are latched immediately, but are not sampled
into the fault register until the following falling edge of AS.
3.4.9. PARITY GENERATION AND CHECKING
The MA31750 features on-chip parity generation and
checking on all data bus transfers. Data generated by the
processor has a parity bit attached to it to allow external logic
to verify write transfers. On read transfers, the processor will
check the incoming parity (if enabled) and will generate the
appropriate parity error fault if detected. However, the data to
be checked is only available as DSN rises at the end of the
cycle so the error flag is generated and latched in the cycle
following the erroneous cycle. Parity checking may be
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