MA31750 Datasheet, PDF (2/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
1. ARCHITECTURE
2. ADDITIONAL FEATURES
The Dynex Semiconducor MA31750 Microprocessor is a
high performance implementation of the MIL-STD-1750A
(Notice 1) Instruction Set Architecture. Figure 1 depicts the
architectural details of the chip. Two key features of this
architecture which contribute to the overall high performance
of the MA31750 are a 32-bit shift network and a 24-bit parallel
multiplier. These sub-systems allow the MA31750 to perform
multi-bit shifts, multiplications,divisions and normalisations in a
fraction of the clock cycles required on machines not having
such resources. This is especially true of floating-point
operations, in which the MA31750 excels. Such operations
constitute a large proportion of the Digital Avionics Instruction
Set (DAIS) mix and generally a high percentage of many signal
processing algorithms, therefore having a significant impact on
system performance.
Key features include:
1) A three-bus (R, S, and Y) datapath consisting of an
arithmetic/logic unit (ALU), three-port register file, shift
network, parallel multiplier and flags block;
2) Four instruction fetch registers C0,C1, IA, and IB;
3) Two operand transfer registers DI, and DO;
4) Two address registers IC and A;
5) A state sequencer;
6) Micro-instruction decode logic.
The relationship between these functional blocks is shown
in Figure 1.
The MA31750 may be operated in one of two basic user
selectable modes. 1750A mode follows the requirements of
MIL-STD-1750A (Notice 1) and implements all of the
mandatory features of this standard. In addition, many of the
optional features such as interval timers A and B, a watchdog
timer and parity checking are included. 1750B mode, when
selected, allows the user access to a range of new instructions
and features as described in the Draft MIL-STD-1750B, Option
2. These include a range of unsigned arithmetic operations
and expanded addressing support instructions.
2.1. MIL-STD-1750 OPTIONAL FEATURES
In addition to implementing all of the required features of
MIL-STD-1750A and the Draft standard MIL-STD-1750B, the
MA31750 also incorporates a number of optional features.
Interval timers A and B as well as a trigger-go counter are
provided. Most specified XIO commands are decoded directly
on the chip and an additional set of commands, associated
with MMU and BPU operations, are also decoded on chip.
2.2. BUS ARBITRATION
The MA31750 has a number of extra control lines to allow
its use in a system utilising multiple processors. A bus request
and grant system coupled with external arbitration logic allows
common data and address buses to be used between devices.
A lock request pin is also provided to allow the processor to
maintain control of the buses when modifying areas of shared
memory.
2.3. MEMORY BLOCK PROTECTION
The basic MMU function allows write or execute protection
to be applied on 4KWord block boundaries. This may be
further resolved to 1kWord blocks by the inclusion of a Block
Protect Unit (BPU). The MA31751 can act as both an MMU
and a BPU in 1750A mode, operating with the full compliment
of 1MWord of memory. It will also support expansion to
8MWord in accordance with Draft MIL-STD-1750B.
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