MA31750 Datasheet, PDF (7/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
3.4.3. MASK REGISTER (MK)
This 16-bit register is used to store the interrupt mask.
Interrupts are masked by ANDing each mask bit with its
corresponding Pl register bit. ie. A logic zero in a given bit
position indicates that the corresponding bit in the Pl register
will be masked. Interrupts which are masked will be captured
in the Pl register but will not be acted on until unmasked.
Interrupt level zero can not be masked.
Linkage
Pointer 0
Service
Pointer 0
CPU status at time
of interrupt
Old Interrupt
Mask
Old Status
Word
3.4.4. PRIORITY ENCODER
This encoder generates an interrupt request to the
sequencer block whenever one or more unmasked interrupts
are pending and enabled in the Pl. The highest priority
unmasked pending interrupt is encoded as a 4-bit vector. This
vector is used during interrupt servicing in order to create the
interrupt linkage and service pointers.
Linkage
Pointer 1
Service
Pointer 1
Old Instruction
Counter
Status at start of
Service Routine
3.4.5. FAULT REGISTER (FT)
This 16-bit register is used to capture and hold both internal
and user implemented external faults using positive logic, i.e.,
a logic one represents a fault. Bus cycle faults are captured at
the end of each machine cycle whilst the two general purpose
faults SYSFN and FLT7N are set when the low time exceeds
the minimum pulse width. Setting any one or more faults in FT
will cause a level 1 (machine error) interrupt request. Once a
fault is set in FT, it may only be cleared via an XIO command.
In 1750B mode, a fault mask register is provided to allow
selective masking of fault conditions. Section 4 (Software
Considerations) contains further information. Figure 27 shows
the fault register assignments.
3.4.6. MEMORY FAULT PAGE AND ADDRESS REGISTERS
These registers capture the page and address information
at the end of each external cycle until a memory fault occurs.
Faults setting bits 0, 1, 2 and 8 in the fault register cause the
registers to stop latching new address information, so retaining
information about the address at which the fault occured. The
registers can be read (using the GPS defined XIOs RMFP and
RMPA). The fault register must be cleared and both memory
fault registers read before latching can restart.
The information stored in the memory fault registers is as
follows:
MFPR[0:3] MFPR[4:7] MFPR[8:10] MFPR[11]
A[0:3] PB[0:3](ASOB)
Res
ION
MFPR[12:15] MFAR[0:15]
AS[0:3]
A[0:15]
Note: MFPR[11] is the
inverse of OIN.
These registers are only available if there is an MMU in the
system. If there is no MMU present, then the RMFP and RMFA
XIO commands become illegal.
The address information held in these registers can be
used to restart code after a memory fault has occurred. Bits
[6:7] of the OAS register store information on the type of
instruction which was being executed when the fault occured:
00 → branch that was taken
01 → single word instruction
10 → double word instruction
(Subtracting this value from the saved address will give the
address of the failed instruction unless it was a branch that
was taken).
Linkage
Pointer 15
Service
Pointer 15
New Interrupt
Mask
New Status
Word
New Instruction
Counter
Figure 11: Interrupt Vectoring
3.4.7. INTERRUPT SERVICING
Nine user interrupt request inputs are provided for
programmed response to asynchronous system events. A low
on any of these inputs will be detected at the rising edge of
CLK (level sensitive interrupts only) and latched into the
Pending Interrupt (Pl) register on the falling edge of CLK at the
end of the current CPU cycle. This sequence occurs whether
interrupts are enabled or disabled or whether the specific
interrupt is masked or unmasked. More details of interrupt
operations are available in Applications Note 4.
All of the user interrupts PWRDN, INT02N - INT15N may
be programmed to be either level or edge sensitive by setting
or clearing the appropriate bit in the system configuration
register. If edge sensitivity is selected then an interrupt request
input must return to the high state before a subsequent request
on that input will be detected. If level sensitivity is selected then
holding an interrupt input low will cause a new interrupt to be
latched following each service. Note that interrupts IOI1N and
IOI2N are level sensitive only.
In order that the system may recognise when a service has
been started, an interrupt acknowledge pin is provided. During
the microcoded interrupt service routine execution, the
processor will read the Linkage Pointer address in memory.
During this operand read cycle, the processor will also assert
INTAKN low, which may be used in conjunction with AS and
address bus bits A[11:14] to reveal the priority level of the
interrupt being serviced. (A[11:14] = 0 indicates level 0
interrupt, A[11:14] = 1 indicates level 1 interrupt, and so on).
INTAKN should also be used to remove level-sensitive
interrupt requests to ensure that repeated requests are not
generated.
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