MA31750 Datasheet, PDF (5/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
3.2. INSTRUCTION EXECUTION
Once initialisation has been completed, the processor will
begin instruction execution. Instruction execution is
characterised by a variety of operations, each is one machine
cycle in duration (two or more system CLK periods).
Depending on the instruction being executed at the time, these
operations include: (1) internal CPU cycles, (2) instruction
fetches, (3) operand transfers, and (4) input/output transfers.
Instruction execution may be interrupted at the end of any
individual machine cycle by an interrupt or Console request.
Internal cycles are always two CLK periods long, whilst the
other cycle types are a minimum of two CLK periods -
extendable by inserting waitstates. In all cycles except internal
cycles, RDN, WRN, DSN and AS strobes are produced to
control the transfer and latching of data and address around
the system.
Cycle Type RD/WRN O/IN
Internal Cycle H
L
Instruction
H
L
Fetch
Operand Read H
H
Operand Write L
H
IO Read
H
H
IO Write
L
H
M/ION
H
H
H
H
L
L
Description
Used to perform all CPU data manipulation operations where bus
activity is not required.
Used to keep the instruction pipeline full with instructions and/or their
postwords. At least one instruction is always ready for execution when
the preceding instruction is completed. During jump and branch
instruction execution the pipeline is refilled by two consecutive
instruction fetches starting at the new instruction location. It is also
refilled as part of interrupt request processing.
Used to read in data from the external system and to write results to the
system.
Input/Output transfers utilize the MIL-STD-1750 XIO and VIO
instructions. RD/WN defines the direction of the transfer. IO transfers
may be divided into three groups; those commands which are
implemented internally by the CPU, those commands which are
implemented by external system hardware and those commands
defined as illegal by MIL-STD-1750A and B.
Figure 7: External Cycle Types
3.3. IO OPERATION
The MA31750 supports a 64KWord addressing space
dedicated to IO control and communication in accordance with
MIL-STD-1750. The control line MION is asserted low when
accessing IO space (see figure 7 above for other strobe
states). One of the two commands XIO or VIO is used to
specify both data for the transfer and the port address (referred
to as an XIO Command in 1750). The CPU contains logic
which decodes all internally supported XIO commands and
generates the control signals necessary to carry out the
commanded action. In addition, the validity of a command not
implemented internally is verified. Figure 20c identifies the XIO
commands which are internally supported by the MA31750.
3.4. INTERRUPT AND FAULT HANDLING
3.4.1. STATUS WORD (SW)
Figure 8 depicts the status register format. This 16-bit word
is divided into four, 4-bit sections. Three of these sections [AS,
PS and, (1750B mode) PB] are control bits for implementing
expanded memory with an external MMU. The fourth section,
CS, is used to hold the carry, positive, zero and negative
condition flags set by the result of the previous arithmetic
operation.
0
34
7 8 11 12 15
CS
R (PB) PS
AS
Field Bits
Description
CS 0
1
2
3
CONDITION STATUS
C- Carry from an addition or no
borrow from a subtraction.
P- Result > 0
Z- Result = 0
N- Result < 0
R
4-7
PB
PS 8-11
RESERVED (=0) in 1750A mode
Page Bank Select in 1750B mode
PROCESSOR STATE:
(a)- Memory access to key code
(b)- Priviledged instruction enable
AS 12-15 ADDRESS STATE:
Page register sets for expanded
memory addressing.
Figure 8: Status Word Format
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