MA31750 Datasheet, PDF (6/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
The AS field is used during expanded memory access to
define the page register set to be used for instruction and
operand memory references. The PS field is used during
memory protect operations to define the access key used for
memory accesses. The PS field is also used during execution
of privileged Instructions - PS must be zero for such operations
to be legal. See Section 4.3 for further information on the use
of this field. The PB field is used in conjunction with the AS
field in 1750B mode to expand the number of page registers
available. Note that attempting to set AS or PB to a non-zero
value with no MMU, or setting PB to a non-zero value in 1750A
mode is illegal. This will be aborted and a fault 11 will be
generated (SW will remain unchanged).
3.4.2. PENDING INTERRUPT REGISTER (PI)
This 16-bit register is used to capture and hold interrupts
until they can be processed by microcode and user software. A
logic 1 is used to represent an active pending interrupt. The Pl
register supports three dedicated external, six user-definable
external, and seven dedicated internal interrupts. Level-
sensitive interrupts are sampled on each rising CLK edge,
whilst edge sensitive interrupts are captured immediately.
System
Interrupts
Internal
Interrupts
PWRD 0 (Cannot be disabled or masked)
1
INT02 2
Machine Error (Cannot be
disabled)
3 Floating-Point Overflow
4 Fixed-Point Overflow
5 Executive call (Cannot be
disabled or masked)
6 Floating-Point Underflow
7 Timer A Overflow
INT08 8
9 Timer B Overflow
INT10 10
INT11 11
IOI1
12
INT13 13
IOI2
14
INT15 15
System
Faults
MPROE (CPU)
MPROE (DMA)
PE (CPU memory)
PE (CPU IO)
PE (DMA)
EXADE or Bus
Timeout (CPU IO)
FLT7
EXADE or Bus
Timeout (CPU
memory)
Reserved
SYSF
EXADE (DMA)
SYSF
Internal
Faults
0
1
2
3
4
5
6 Parallel IO Transfer Error
7
8
9 Illegal Instruction Opcode
10 Priviledged Instruction
11 Unimplemented Address State
12
13 MA31750 BIT Fail
14
15
Figure 9: Pending Interrupt Bit Assignments
Figure 10: Fault Register Bit Assignments
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