MA31750 Datasheet, PDF (3/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
3. MODES OF OPERATION
MA31750 operating modes include: (1) initialisation, (2)
instruction execution, (3) interrupt servicing, (4) fault servicing,
(5) timer operations and (6) console operation.
3.1. INITIALISATION
The MA31750 executes a microcoded initialisation routine
in response to a hardware reset or power-up. Figure 3 shows
a cycle-by-cycle breakdown of this routine. The operations
performed are dependent on the system configuration read by
the processor during startup. Figure 2 summarises the
resulting initialisation state.
MA31750
Instruction Counter
Status Word
Fault Register Zero
Fault Mask Register (1750B)
Pending Interrupt Register
Interrupt Mask Register
General Registers
Interrupts
Timers A and B
Timer Reset Registers (1750B)
Trigger-Go Counter
TGON Line
Start-Up ROM
DMA
Zero
Zero
Zero
All ones
Zero
Zero
Undefined
Disabled
Zeroed and started
Zero
Reset and started
High
Enabled
Disabled
MMU
Page Registers AL/W/E fields
Page Register PPA field
Zero
Logical to physical
BPU
Memory Protect RAM
Global Memory Protect
Zero (disabled)
Enabled
Figure 2: Initialization State
The last action performed by the initialisation routine is to
load the instruction pipeline. Instruction fetches start at
memory location zero with AS = 0, PS = 0 and PB = 0 and will
be from the Start-Up ROM (SUR) if implemented. Whether
BIT passes or not, the processor will begin instruction
execution at this point. The system start-up code may include
a routine to enable and unmask interrupts in order to detect
and respond to a BIT failure if required.
Addr Operation
0
PIC initialised
1
A<-- 0x8410
*2
Read external configuration register from 8410H
(CONFWN asserted low)
3
-
1F
-
20
If BPU, N<-- 128 else N<-- 0
21
Decrement N; branch to 21 if N >= 0
4
Write internal configuration register
5
-
6
If no MMU, br to 7
13
-
14
-
15
N <-- 256
16
Decrement N
*17
Write MMU Instruction Page Register N
*18
Write MMU Operand Page Register N; branch to 16 if
N>0
19
A <-- 0400H
1A
N <-- 16
1B
PBSR <-- N
1C
-
*1D
Write Memory control register to MMU with PB = N
1E
Decrement N; branch if N >= 0 to 1B
7
A <-- 0
8
IC <-- A
9
Br to BIT if required
A
-
B
Br if no SUR to 00D
C
-
D
Re-init PIC
E
-
*F
Zero SW
10
-
32
-
33
Br to 011 if BIT passed (or not run)
34
35
36
Set FT bit 13
11
Init DMAE, SUREN, NPU
12
*3F8 Fetch first word from 0
*3F9 Fetch second word from 1
First instruction first cycle
* Indicates an external cycle
Figure 3: Initialization Sequence
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