MA31750 Datasheet, PDF (35/42 Pages) Dynex Semiconductor – High Performance MIL-STD-1750 Microprocessor

MA31750
P in Na me Func t ion
Description
BUS ARBI TRATI ON
LOCKN
Bus Lock
Request.
Active LOW
REQN
GRANTN
Bus Request.
Active LOW
Bus Grant.
Active LOW
This active-low output signal indicates to the bus arbiter that the processor is performing an
atomic instruction which should not be interrupted. External bus accesses should be
denied whilst LOCKN is low. The CPU will lock the bus during read-modify-write instructions
such as DECM (Decrement Memory) and TSB (Test & Set Bit). LOCKN remains high during
non-locked cycles. This signal is tri-stated on cycles not assigned to this CPU.
Not e : LOCKN is advisory only - it may be ignored by the arbiter if neccessary.
This active-low output signal is driven low when the CPU requires the bus in the next cycle.
This signal may be used as an input to an external bus arbiter. The signal becomes invalid
once the CPU has started the requested cycle.
This active-low signal is asserted by an external bus arbiter to indicate that the CPU
currently has the highest priority bus request. The CPU will begin a bus cycle (if one is
pending) commencing with the next CPU clock cycle.
I NTERRUPTS
PWRDN
Power-Down
Interrupt.
Active LOW
INT02N,
Interrupt Inputs.
INT08N,
Active LOW
INT10N,
INT11N,
INT13N,
INT15N
IOI1N, IOI2N
INTAKN
Interrupt
Acknowledge
Strobe.
Active LOW
A low on this active low input will be captured in the PI register and sets Pending Interrupt 0.
This is the highest priority interrupt and cannot be masked or disabled.
A low on any of these active low inputs will be captured in the Pl register and will set
Pending Interrupt levels 2, 8, 10, 11, 13, and 15, respectively. Level 2 is the highest priority
user level, while level 15 is the lowest priority. These interrupts are maskable and can be
disabled. If edge sensitivity has been selected, interrupts will be captured on the falling
edge of the interrupt input, otherwise the interrupt will be latched by the falling edge of CLK
at the end of the machine cycle.
Not e : Interrupt levels 1, 3, 4, 5, 6, 7 and 9 are dedicated to internal machine interrupts.
A low on either input will set Pending Interrupt levels 12 or 14 respectively. These inputs
are level sensitive only and are captured by the falling edge of CLK at the end of a machine
cycle. These inputs can be masked and disabled.
This active-low output indicates the start of an interrupt service. When low, the processor
outputs the Linkage Pointer (LP) address to the system. The INTAKN signal may be used to
remove level-sensitive interrupt inputs: the current interrupt priority can be ascertained by
reading the address bus during the cycle in which this output is low.
FAULTS
MPROEN Memory Protect A low on this input, sampled on falling AS, indicates that an execute protect or write
Fault.
protect fault has been detected. Bit 0 of the fault register is set if this signal is applied
Active LOW
during a CPU cycle; bit 1 is set if the line goes low during a DMA cycle. Either condition sets
Pending Interrupt level 1. The CPU will prevent access to memory (by inhibiting strobe
production) whilst this input is LOW. See 3.4.7.1. To effectively use this feature, MPROEN
should be pulled low prior to the start of the next machine cycle.
PEN
Parity Error
A low on this active-low input, sampled on falling AS, informs the CPU that an external
Active LOW
parity error has occurred. Bit 2 (memory), 3 (IO) or 4 (DMA) of the Fault Register is set,
depending upon the type of transfer taking place. This asserts a level 1 Pending Interrupt.
EXADEN External Address A low on this active-low input, sampled on falling AS, informs the CPU that an external
Error
address error has occurred. Bit 8 of the fault register is set if this signal goes low during a
Active LOW
memory cycle; bit 5 is set if the signal goes low during an IO cycle and bit 14 is set if a DMA
has control of the system. Either error condition asserts a level 1 pending interrupt. As with
MPROEN, the CPU will prevent access to memory (by inhibiting strobe production) whilst
this input is LOW. See 3.4.8.1
FLT7N
Fault Level 7
A low at any time on this active-low input sets bit 7 of the fault register, causing a level 1
Active LOW
pending interrupt. This fault is user- definable.
SYSFN
System Fault
A low at any time on this active-low input sets bits 13 and 15 of the fault register, causing a
Active LOW
level 1 pending interrupt. This fault is user definable.
BUSFAULTN Illegal address This active-low output drops low if any bus-related fault (MPROEN, EXADEN or PEN) is
Active LOW
detected low or if the bus fault timeout circuit causes an interface timeout.
Figure 39 (continued): Pin Descriptions
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